The present invention relates to a large capacity and high speed semiconductor memory.
Dynamic memories have high bit density because each memory cell is constituted by two elements comprising a transfer FET (Field Effect Transistor) and a storage capacitor. Accordingly, the dynamic memories can provide a bit density three times higher than that of static memories, e.g., with a memory cell comprising six elements. For this reason, dynamic memories are mainly used for large capacity semiconductor memories.
However, with dynamic memories, it is necessary to effect a refresh operation at predetermined time periods in order to latch memory contents stored therein. Accordingly, the number of the maximum cycle is limited at a page mode operation in which column addresses are sequentially changed to effect a read/write operation in respect to the same row.
One type of dynamic memory is shown, for instance, in "64K bit MOS dynamic RAM having Auto/Self Reflesh function" (Electro-communication society Review Vol. J66-C (No. 1), PP 62-69, January 1983, particularly 2-3 self-refresh operation left column, P. 65). Dynamic memory of this type is provided therein with a timer and a refresh counter to effect a self-reflesh operation with information fed from the refresh counter which is counted up by the timer. However, with this semiconductor memory, since sense amplifiers are used for refresh operation at a self-refresh time period, it is not possible to effect a read/write operation by externally designating an address not only in the row direction but also in the column direction during a self-refresh time period.
Further, in F. Baba et al. "A 35ns 64K Static Column DRAM", Digest of Technical Papers of 1983 IEEE International Solid-State Circuits Conference, pp. 64-65, Feb. 1983, a dynamic memory comprising static column address circuits and an address transition detecting circuit is described. The dynamic memory of this type effects column address selection after a row address is selected in the same manner as conventional static memories. Without a column address strobe signal, a read operation with respect to different column addresses is possible, resulting in high speed operation. However, with this dynamic memory cell, it is not possible to effect a write operation at a high speed and to effect a read/write operation during a refresh time period.
The drawbacks with such prior art semiconductor memories are pointed as follows:
(1) Since parasitic capacitance between a bit line and a data line is large, long access time and cycle time for a read/write operation, and long cycle time for a page mode are required, resulting in low speed operation.
(2) There exists a maximum value in connection with the number of refresh cycles at a page mode with respect to a change of column address effected when row addresses are fixed.
(3) It is impossible to perform the access for read/write operations with respect to the memory during a self-refresh operation.
(4) It is necessary to repeatedly effect a row selecting operation every a certain repetition of page mode cycles although the same row is accessed, resulting in large power consumption.